1 Field of the Invention
The present invention relates generally to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device by taking advantage of the presence/absence of an electrical conduction between an underlying interconnection pattern of a contact hole and a substrate. The present invention also relates to a method of manufacturing a semiconductor device by taking advantage of the fact that there is a difference in etch selectivity between an oxide film and an underlying interconnection pattern thereunder according to the area of the underlying interconnection pattern.
2 Description of the Background Art
A method of manufacturing a conventional semiconductor device, such as a fuse element, will be described with reference to FIG. 13.
Referring to FIG. 13, a lower interlayer insulating film 1 is formed on a semiconductor substrate 100. An interconnection layer 3 is formed on lower interlayer insulating film 1. An upper interlayer insulating film 6 is formed on lower interlayer insulating film 1 to cover interconnection layer 3. Formed in upper interlayer insulating film 6 is a contact hole 4 reaching interconnection layer 3. Contact hole 4 is formed so that etching will stop at the top surface of interconnection layer 3. A plug 5, which is to be a conductive member, is filled in contact hole 4. Upper interconnection layers 7a, 7b, connected to respective plugs 5, are formed on upper interlayer insulating film 6. Although not shown, upper interconnection layer 7a is connected to a first circuit, upper interconnection layer 7b to a second circuit. The first circuit and the second circuit are electrically isolated from each other by cutting off interconnection layer 3 therebetween.
In the semiconductor device, interconnection layer 3 is electrically conducted to upper interconnection layers 7a, 7b, respectively, via plug 5. In such a structure, the smaller the radius of contact hole 4 becomes, the smaller the contact area between interconnection layer 3 and plug 5 will be, which leads to an increased contact resistance.
Now, a method of manufacturing a conventional semiconductor device, such as a dynamic random access memory, will be described.
Referring to FIG. 14, an interlayer insulating film 1a is formed on a semiconductor substrate 100. A lower interconnection layer 10 is formed on interlayer insulating film 1a. An interlayer insulating film 1b is formed on interlayer insulating film 1a to cover lower interconnection layer 10. By photolithography and etching, in interlayer insulating films 1a and 1b, a first connection hole 11 is formed to reach semiconductor substrate 100. A photoresist, which was used as a mask in the photolithography, is then removed. Formed on interlayer insulating film 1b is a first storage node electrode 12 electrically connected to semiconductor substrate 100 through first connection hole 11. To form first storage node electrode 12, a polycrystalline silicon film is first formed on semiconductor substrate 100, which is then patterned by photolithography and dry etching. A photoresist used as a mask is then removed. An interlayer insulating film 1c is formed on interlayer insulating film 1b to cover first storage node electrode 12. Utilizing the photolithography and etching again, a second connection hole 14a is formed to make an electrical conduction between first storage node electrode 12 and a second storage node electrode as described below.
Referring to FIG. 15, a polycrystalline silicon film is formed for the formation of second storage node electrode 13a, which is subjected to photolithography and then patterned by dry etching in the manner as described above. The photoresist used as a mask is now removed. An interlayer insulating film 1d is formed on interlayer insulating film 1c to cover second storage node electrode 13a. By photolithography and etching, a second connection hole 14b is formed to achieve an electrical conduction between second storage node electrode 13a and a third storage node electrode as described below.
Referring to FIGS. 15 and 16, another polycrystalline silicon film is formed, subjected to photolithography, and patterned by dry etching in the manner as described above to form the third storage node electrode 13b.
FIG. 17 is a cross sectional view of a conventional static random access memory, which will be described later.
In the conventional method of manufacturing a dynamic random access memory, the following series of steps are repeated for each fin: forming an interlayer insulating film; performing photolithography; etching to form a connection hole; forming a polycrystalline silicon film; performing photolithography; and etching to form a storage node electrode. Thus a large number of process steps are required. This results in poor efficiency in manufacturing, and thus decreases the yield of the device.
In the conventional method of manufacturing a semiconductor device, besides the problem regarding manufacturing methods of the aforementioned fuse element, dynamic random access memory (DRAM) and static random access memory (SRAM), there is another problem in measuring thickness of a gate oxide film. The thickness of a gate oxide film or the like has been conventionally measured using an optical measuring device such as an ellipsometer. With the increasing demand for a thinner gate film, however, it has been found that such an optical measuring device cannot provide a reliable measurement value for a film less than 3 nm thick. There has been another way of accurately measuring the thickness of a thin oxide film, which is to examine the cross section of the film by a transmission electron microscope (TEM). This, however, takes a relatively long time for examining a single point, and is therefore not effective when there exist a number of measuring points such as the case where the distribution of film thickness in a wafer surface is to be examined.